Integrated memory may utilize access transistors having vertical pillar-type active regions. In some applications, bitlines may extend beneath the active regions and wordlines may extend along the active regions. The wordlines may comprise segments serving as gate electrodes, with such segments being spaced from the active regions by gate dielectric. A problem with such architectures is that it is difficult to scale the architectures into higher densities of integration. Specifically, the spacing between neighboring active regions becomes narrower as the architectures are downscaled. Accordingly, the wordlines formed between the neighboring active regions become narrower, which increases wordline resistance. Also, tighter packing of the wordlines and access transistors may increase disturbance between neighboring access transistors.
Shield lines may be introduced in an attempt to reduce disturbance between neighboring access transistors. However, the shield lines may consume valuable real estate between adjacent access transistors and thereby further reduce space available for the wordlines, resulting in even narrower wordlines with even higher resistance.
It would be desirable to develop new architectures for integrated memory which alleviate or prevent the above-described problems.